The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Sep. 11, 2007
Applicants:

Joong-chul Yoon, Seocho-gu, KR;

Seong-hyun Kim, Yongin-si, KR;

Sung-hyun Kim, Anyang-si, KR;

Sang-bum Kim, Suwon-si, KR;

Sang-wook Kang, Seocho-gu, KR;

Chul-joon Choi, Suwon-si, KR;

Jong-sang Choi, Seongnam-si, KR;

Koon-han Sohn, Yongin-si, KR;

Byung-yoon Kang, Suwon-si, KR;

Inventors:

Joong-Chul Yoon, Seocho-gu, KR;

Seong-Hyun Kim, Yongin-si, KR;

Sung-hyun Kim, Anyang-si, KR;

Sang-Bum Kim, Suwon-si, KR;

Sang-Wook Kang, Seocho-gu, KR;

Chul-Joon Choi, Suwon-si, KR;

Jong-Sang Choi, Seongnam-si, KR;

Koon-Han Sohn, Yongin-si, KR;

Byung-Yoon Kang, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04K 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.


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