The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Feb. 28, 2006
Applicants:

Hong-fei LU, Matsumoto, JP;

Shinichi Jimbo, Ishikawa-gun, JP;

Inventors:

Hong-fei Lu, Matsumoto, JP;

Shinichi Jimbo, Ishikawa-gun, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
Abstract

To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator regiondisposed between an n-type drift layerand a first n-type regionabove n-type drift layer, facilitates limiting the emitter hole current, preventing latch-up from occurring, raising neither on-resistance nor on-voltage. The semiconductor device according to the invention, which includes a p-type regiondisposed between the buried insulator regionand n-type drift layer, facilitates depleting n-type drift layerin the OFF-state of the device. The semiconductor device according to the invention, which includes a second n-type regiondisposed between the first n-type regionand the n-type drift layer, facilitates dissipating the heat caused in the channel region or in the first n-type regionto a p-type collector layer, which is a semiconductor substrate, via the second n-type region, n-type drift layerand an n-type buffer layer


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