The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Nov. 07, 2008
Applicants:

Byoung-ho Kwon, Hwaseong-si, KR;

Sang-youn JO, Suwon-si, KR;

Jin-sook Choi, Suwon-si, KR;

Chang-ki Hong, Seongnam-si, KR;

Bo-un Yoon, Seoul, KR;

Hong-soo Kim, Yongin-si, KR;

Se-rah Yun, Seoul, KR;

Inventors:

Byoung-ho Kwon, Hwaseong-si, KR;

Sang-youn Jo, Suwon-si, KR;

Jin-sook Choi, Suwon-si, KR;

Chang-ki Hong, Seongnam-si, KR;

Bo-un Yoon, Seoul, KR;

Hong-soo Kim, Yongin-si, KR;

Se-rah Yun, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.


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