The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Apr. 05, 2007
Applicants:

Woo-sik Jun, Suwon-si, KR;

Kyung-jin Yoo, Suwon-si, KR;

Choong-youl Im, Suwon-si, KR;

Jong-hyun Choi, Suwon-si, KR;

Do-hyun Kwon, Suwon-si, KR;

Inventors:

Woo-Sik Jun, Suwon-si, KR;

Kyung-Jin Yoo, Suwon-si, KR;

Choong-Youl Im, Suwon-si, KR;

Jong-Hyun Choi, Suwon-si, KR;

Do-Hyun Kwon, Suwon-si, KR;

Assignee:

Samsung Mobile Display Co., Ltd., Giheung-Gu, Yongin, Gyunggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a thin film transistor (TFT) panel, a method of fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT panel has a TFT region and a capacitor region. A TFT is formed in the TFT region and a capacitor is formed in the capacitor region. The TFT includes an active layer that includes a source and a drain regions. A gate insulation layer is formed on the active layer, and a gate electrode is formed on the gate insulation layer over the active layer. A source and a drain electrodes are formed over the active layer, and connected to the source and drain regions, respectively. In the TFT region, an interlayer insulation layer is formed between the gate electrode and the source/drain electrodes. In the capacitor region, an interlayer insulation layer is formed between a capacitor lower electrode and a capacitor upper electrode to form a capacitor. The interlayer insulation layers of the TFT region and the capacitor region have different layer structures and have different dielectric constants. Therefore, the capacitor region can have higher capacitance while the TFT region can have lower capacitance to reduce parasitic capacitance.


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