The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2011

Filed:

Aug. 29, 2008
Applicants:

Ji-hyun Jung, Gwangju-si, KR;

Shi-yun Cho, Anyang-si, KR;

Young-min Lee, Yongin-si, KR;

Youn-ho Choi, Seoul, KR;

Inventors:

Ji-Hyun Jung, Gwangju-si, KR;

Shi-Yun Cho, Anyang-si, KR;

Young-Min Lee, Yongin-si, KR;

Youn-Ho Choi, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Maetan-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

An IC package includes: a multi-layered PCB having a plurality of insulating layers and a plurality of conductive pattern layers stacked in sequence and a plurality of via-holes formed through the plurality of the insulating layers for an electrical connection between the layers; and an IC chip disposed in a core insulating layer of the plurality of the insulating layers to be embedded in the multi-layered PCB and including a plurality of input/output pads on their surface. The input/output pads disposed at an outermost area of the IC chip are coupled to outer terminals by connection members without passing through said via-hole, the remaining input/output pads except for the input/output pads disposed at the outermost area of the IC chip are coupled to the outer terminals through the via-hole.


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