The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2011
Filed:
Apr. 25, 2008
Nam Gyu Ryu, Chungcheongbuk-do, KR;
Ho Ryong Kim, Chungcheongbuk-do, KR;
Won John Choi, Chungcheongbuk-do, KR;
Jae Hwan Kim, Chungcheongbuk-do, KR;
Seoung Hyun Kang, Chungcheongbuk-do, KR;
Young Hee Yoon, Gyeonggi-do, KR;
Nam Gyu Ryu, Chungcheongbuk-do, KR;
Ho Ryong Kim, Chungcheongbuk-do, KR;
Won John Choi, Chungcheongbuk-do, KR;
Jae Hwan Kim, Chungcheongbuk-do, KR;
Seoung Hyun Kang, Chungcheongbuk-do, KR;
Young Hee Yoon, Gyeonggi-do, KR;
Hynix Semiconductor Inc., Kyoungki-do, KR;
Abstract
A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.