The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8051273 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 01, 2011

Filed:

Nov. 02, 2010
Applicant:

Shorin Kyo, Tokyo, JP;

Inventor:

Shorin Kyo, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the PEs, where P<S, operate as an instruction cache. The remaining memories operate as data memories or as data cache memories. One out of S sets of general-purpose registers, inherently belonging to the PEs, directly operates as a general register group for the PU. Out of the remaining S−1 sets, T set or a required number of sets, where T<S−1, are used as storage registers that store tags of the instruction cache.


Find Patent Forward Citations

Kyo, Shorin. (2011). Supplying instruction stored in local memory configured as cache to peer processing elements in mimd processing units (U.S. Patent No. 8051273). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8051273

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