The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2011
Filed:
Sep. 15, 2006
Jayanta Bhadra, Austin, TX (US);
Magdy S. Abadir, Austin, TX (US);
Ping Gao, Wynn Vale, AU;
Timothy David Mcdougall, Tranmere North, AU;
Jayanta Bhadra, Austin, TX (US);
Magdy S. Abadir, Austin, TX (US);
Ping Gao, Wynn Vale, AU;
Timothy David McDougall, Tranmere North, AU;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.