The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2011
Filed:
Feb. 25, 2009
Ruigang LI, Austin, TX (US);
David Donggang Wu, Austin, TX (US);
James F. Buller, Austin, TX (US);
Jingrong Zhou, Austin, TX (US);
Ruigang Li, Austin, TX (US);
David Donggang Wu, Austin, TX (US);
James F. Buller, Austin, TX (US);
Jingrong Zhou, Austin, TX (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
A transistor-based fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.