The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2011

Filed:

Jan. 23, 2009
Applicants:

Yeh-ning Jou, Taipei County, TW;

Shang-hui Tu, Tainan, TW;

Jui-chun Chang, Hsinchu, TW;

Chen-wei Wu, Hsinchu, TW;

Inventors:

Yeh-Ning Jou, Taipei County, TW;

Shang-Hui Tu, Tainan, TW;

Jui-Chun Chang, Hsinchu, TW;

Chen-Wei Wu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/93 (2006.01);
U.S. Cl.
CPC ...
Abstract

Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A Pdoped drain region is disposed in the high-V N-well. A Pdiffused region and an Ndoped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the Ndoped source region and the other end extending over the insulation region.


Find Patent Forward Citations

Loading…