The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2011
Filed:
Apr. 14, 2008
Chantal Combi, Oggiono, IT;
Benedetto Vigna, Potenza, IT;
Federico Giovanni Ziglioli, Gessate, IT;
Lorenzo Baldo, Bareggio, IT;
Manuela Magugliani, Cornaredo, IT;
Ernesto Lasalandra, San Donato Milanese, IT;
Caterina Riva, Cusago, IT;
Chantal Combi, Oggiono, IT;
Benedetto Vigna, Potenza, IT;
Federico Giovanni Ziglioli, Gessate, IT;
Lorenzo Baldo, Bareggio, IT;
Manuela Magugliani, Cornaredo, IT;
Ernesto Lasalandra, San Donato Milanese, IT;
Caterina Riva, Cusago, IT;
STMicroelectronics S.r.l., Agrate Brianza, IT;
Abstract
A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.