The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2011

Filed:

Aug. 28, 2009
Applicants:

Xiangdong Chen, Irvine, CA (US);

Bruce Chih-chieh Shen, Irvine, CA (US);

Henry Kuo-shun Chen, Irvine, CA (US);

Inventors:

Xiangdong Chen, Irvine, CA (US);

Bruce Chih-Chieh Shen, Irvine, CA (US);

Henry Kuo-Shun Chen, Irvine, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.


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