The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8046565 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 25, 2011

Filed:

Dec. 05, 2007
Applicant:

Hideki Yasukawa, Kanagawa, JP;

Inventor:

Hideki Yasukawa, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/16 (2006.01); G06F 9/46 (2006.01); G06F 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods for accelerators which may execute a program in conjunction with a PC are disclosed. In one embodiment, an accelerator includes a plurality of calculation units, each calculation unit operable to execute the program in parallel, an operation control unit configured to control an operation capability or a processing capability of at least one of the plurality of calculation units, and a control unit configured to determine a corresponding operation capability or processing capability for the plurality of calculation units based on load information on the program to be executed and control the operation control unit accordingly.


Find Patent Forward Citations

Yasukawa, Hideki. (2011). Accelerator load balancing with dynamic frequency and voltage reduction (U.S. Patent No. 8046565). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8046565

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