The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2011

Filed:

Dec. 06, 2010
Applicants:

Takashi Sasabayashi, Kawasaki, JP;

Arihiro Takeda, Sagamihara, JP;

Hiroyasu Inoue, Kawasaki, JP;

Kazuya Ueda, Kawasaki, JP;

Yoshio Koike, Kawasaki, JP;

Hideaki Tsuda, Kawasaki, JP;

Yasutoshi Tasaka, Kawasaki, JP;

Hidefumi Yoshida, Kawasaki, JP;

Kunihiro Tashiro, Kawasaki, JP;

Tsuyoshi Kamada, Kawasaki, JP;

Kimiaki Nakamura, Kawasaki, JP;

Inventors:

Takashi Sasabayashi, Kawasaki, JP;

Arihiro Takeda, Sagamihara, JP;

Hiroyasu Inoue, Kawasaki, JP;

Kazuya Ueda, Kawasaki, JP;

Yoshio Koike, Kawasaki, JP;

Hideaki Tsuda, Kawasaki, JP;

Yasutoshi Tasaka, Kawasaki, JP;

Hidefumi Yoshida, Kawasaki, JP;

Kunihiro Tashiro, Kawasaki, JP;

Tsuyoshi Kamada, Kawasaki, JP;

Kimiaki Nakamura, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A liquid crystal display including two substrates, gate bus lines, liquid crystal molecules, and a polymer that determines directions in which the liquid crystal molecules tilt. A plurality of divisional areas are arranged on one of the substrates. The pixels are aligned in a column between drain bus lines. A pixel electrode is formed at each of the divisional areas. A first thin film transistor drives a first divisional area, and a second thin film transistor drives a second divisional area of the same column. The first and second thin film transistors are electrically connected to the same gate bus line. Either the pixel electrodes formed at each of the divisional areas are electrically insulated from each other, or they are connected to each other through a high resistance. A first threshold voltage within the first divisional area is different from a second threshold voltage of the second divisional area.


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