The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2011
Filed:
May. 16, 2005
Ramnath Venkatraman, San Jose, CA (US);
Carl Anthony Monzel, Iii, Eagan, MN (US);
Subramanian Ramesh, Cupertino, CA (US);
Ramnath Venkatraman, San Jose, CA (US);
Carl Anthony Monzel, III, Eagan, MN (US);
Subramanian Ramesh, Cupertino, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.