The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2011
Filed:
May. 19, 2009
Arvind Sundararajan, Sunnyvale, CA (US);
Haibing MA, Superior, CO (US);
Andrew Dow, Edinburgh, GB;
Singh Vinay Jitendra, Fremont, CA (US);
Arvind Sundararajan, Sunnyvale, CA (US);
Haibing Ma, Superior, CO (US);
Andrew Dow, Edinburgh, GB;
Singh Vinay Jitendra, Fremont, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Design synchronization for a High-Level Modeling System ('HLMS') of an integrated circuit device ('IC') is described. In a method for generating a netlist, a description of a first circuit block of a user design is input to a programmed computer system programmed with a computer-aided modeling system. The description includes output port information of the first circuit block and synchronization signal information. The computer-aided modeling system selects a circuit core for the first circuit block responsive to output port information and the synchronization signal information, the circuit core including port metadata. The computer-aided modeling system selects at least one macro responsive to the port metadata for generation of the netlist. The macro is for rate synchronized coupling of the first circuit block to a second circuit block of the user design. The computer-aided modeling system outputs the netlist including the macro.