The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2011
Filed:
Jun. 28, 2007
Luis A. Lastras-montano, Cortlandt Manor, NY (US);
James A. O'connor, Ulster Park, NY (US);
Luiz C. Alves, Hopewell Junction, NY (US);
William J. Clarke, Poughkeepsie, NY (US);
Timothy J. Dell, Colchester, VT (US);
Thomas J. Dewkett, Staatsburg, NY (US);
Kevin C. Gower, LaGrangeville, NY (US);
Luis A. Lastras-Montano, Cortlandt Manor, NY (US);
James A. O'Connor, Ulster Park, NY (US);
Luiz C. Alves, Hopewell Junction, NY (US);
William J. Clarke, Poughkeepsie, NY (US);
Timothy J. Dell, Colchester, VT (US);
Thomas J. Dewkett, Staatsburg, NY (US);
Kevin C. Gower, LaGrangeville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.