The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2011

Filed:

Aug. 04, 2008
Applicants:

Michael Bruennert, Munich, DE;

Peter Gregorius, Munich, DE;

Georg Braun, Holzkirchen, DE;

Andreas Gaertner, Munich, DE;

Hermann Ruckerbauer, Moos, DE;

George Alexander, Durham, NC (US);

Johannes Stecker, Munich, DE;

Inventors:

Michael Bruennert, Munich, DE;

Peter Gregorius, Munich, DE;

Georg Braun, Holzkirchen, DE;

Andreas Gaertner, Munich, DE;

Hermann Ruckerbauer, Moos, DE;

George Alexander, Durham, NC (US);

Johannes Stecker, Munich, DE;

Assignee:

Qimonda AG, München, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.


Find Patent Forward Citations

Loading…