The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2011
Filed:
Jul. 11, 2006
Takahiko Murata, Osaka, JP;
Takumi Yamaguchi, Kyoto, JP;
Shigetaka Kasuga, Osaka, JP;
Takayoshi Yamada, Osaka, JP;
Takahiko Murata, Osaka, JP;
Takumi Yamaguchi, Kyoto, JP;
Shigetaka Kasuga, Osaka, JP;
Takayoshi Yamada, Osaka, JP;
Panasonic Corporation, Osaka, JP;
Abstract
An object of the present invention is to provide a two-dimensional solid state imaging device which can realize speeding up of signal output. The two-dimensional solid state imaging device includes: a pixel region; a first capacitance element and a second capacitance element each of which is arranged for a different column of pixels and accumulates pixel signals of the corresponding column of pixels; a first horizontal signal line and a second horizontal signal line each of which transmits the pixel signals accumulated in a corresponding capacitance element; a common signal line connected to the horizontal signal lines; a scan timing generation unit and a switch unit which control readout of the pixel signals from the capacitance element to the horizontal signal line; and an external output timing unit and a switch unit which select the horizontal signal line and control output of the pixel signals from the selected horizontal signal line to the common signal line. Here, the scan timing generation unit and the switch unit, and the external output timing unit and the switch unit control the readout and the output of the pixel signals, respectively, so that a time period required for the readout of the pixel signals from the capacitance element to the signal line is longer than a time period required for the output of the pixel signals from the signal line to the common signal line.