The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2011

Filed:

Sep. 03, 2009
Applicants:

Ivan Milosavljevic, Thousand Oaks, CA (US);

Adele Schmitz, Thousand Oaks, CA (US);

Michael Antcliffe, Los Angeles, CA (US);

Ming HU, Cerritos, CA (US);

Lorna Hodgson, Cornelius, NC (US);

Inventors:

Ivan Milosavljevic, Thousand Oaks, CA (US);

Adele Schmitz, Thousand Oaks, CA (US);

Michael Antcliffe, Los Angeles, CA (US);

Ming Hu, Cerritos, CA (US);

Lorna Hodgson, Cornelius, NC (US);

Assignee:

HRL Laboratories, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/96 (2006.01);
U.S. Cl.
CPC ...
Abstract

In various embodiments, a tiered gate structure transistor is provided including a source, a drain, and a gate between the source and the drain. The tiered gate structure transistor including a gate foot having a top portion and sidewalls. A gate head is attached to the top portion of the gate foot. A passivation layer extends along and directly contacts an uppermost surface of the source, and extends along and directly contacts an uppermost surface of the drain, the passivation layer surrounds the sidewalls of the gate foot such that the top portion is not covered by the passivation layer and such that the passivation layer surrounding the sidewalls supports the gate head.


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