The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2011
Filed:
Aug. 12, 2002
Michael J. Haji-sheikh, Dekalb, IL (US);
James R. Biard, Richardson, TX (US);
James K. Guenter, Garland, TX (US);
Bobby M. Hawkins, Wylie, TX (US);
Michael J. Haji-Sheikh, Dekalb, IL (US);
James R. Biard, Richardson, TX (US);
James K. Guenter, Garland, TX (US);
Bobby M. Hawkins, Wylie, TX (US);
Finisar Corporation, Sunnyvale, CA (US);
Abstract
Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer () having a substrate (), at least one active layer () and at least one surface layer (), Current control can be achieved through the formation of patterns () surrounding contacts (), said patterns () including insulating implants and/or sacrificial layers formed between active devices represented by said contacts (). Current flows through active regions () associated with said contacts () and active devices. Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Current control at the wafer level is important when using WLBI methods and systems.