The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2011

Filed:

Dec. 19, 2008
Applicants:

Takumi Hasegawa, Tachikawa, JP;

Motoyuki Sato, Ome, JP;

Tomoji Nakamura, Fussa, JP;

Nobuo Konami, Hamura, JP;

Jun Matsushima, Sagamihara, JP;

Inventors:

Takumi Hasegawa, Tachikawa, JP;

Motoyuki Sato, Ome, JP;

Tomoji Nakamura, Fussa, JP;

Nobuo Konami, Hamura, JP;

Jun Matsushima, Sagamihara, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.


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