Arbitrating cache misses in a multithreaded/multi-core processor

Abstract

In one embodiment, a processor comprises a cache and a cache miss unit coupled to the cache. The cache is coupled to be accessed by cache accesses corresponding to a plurality of threads active in the processor. The cache miss unit is configured to record a plurality of cache misses detected in the cache and to associate each cache miss of the plurality of cache misses with a corresponding thread of the plurality of threads for which that cache miss is detected. Additionally, the cache miss unit is configured to initiate a cache fill for a selected cache miss of the plurality of cache misses. The cache miss unit is configured to select the selected cache miss based on a prioritization of the corresponding threads associated with the plurality of cache misses. In one implementation, the cache is an instruction cache and the cache misses are due to fetches corresponding to the plurality of threads.