The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2011

Filed:

Apr. 09, 2008
Applicants:

Eric Quinnell, Austin, TX (US);

Earl E. Swartzlander, Jr., Austin, TX (US);

Carl Lemonds, Austin, TX (US);

Inventors:

Eric Quinnell, Austin, TX (US);

Earl E. Swartzlander, Jr., Austin, TX (US);

Carl Lemonds, Austin, TX (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/483 (2006.01);
U.S. Cl.
CPC ...
Abstract

A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed.


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