Clock and data recovery circuit and method of recovering clocks and data

Abstract

A clock and data recovery circuit that does not use a reference clock and a method of recovering cocks and data, in which the clock and data recovery circuit includes a clock generation unit, a mirror delay unit, a preamble phase detection unit, and a sampling unit. The clock generation unit generates a clock signal such that a phase of the clock signal is locked to a phase of a data signal inputted to the clock generation unit. The mirror delay unit outputs a plurality of delayed preamble signals based on the preamble signal during a preamble period. The preamble phase detection unit provides the charge pump with a preamble phase detection signal having information on a phase difference between the preamble signal and the clock signal during the preamble period. The sampling unit extracts data from the data signal by sampling the data signal with the clock signal.