The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2011
Filed:
Sep. 30, 2008
Brian A. Winstead, Austin, TX (US);
Gowrishankar L. Chindalore, Austin, TX (US);
Konstantin V. Loiko, Austin, TX (US);
Horacio P. Gasquet, Austin, TX (US);
Brian A. Winstead, Austin, TX (US);
Gowrishankar L. Chindalore, Austin, TX (US);
Konstantin V. Loiko, Austin, TX (US);
Horacio P. Gasquet, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate.