The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2011

Filed:

May. 30, 2008
Applicants:

David W. Boerstler, Round Rock, TX (US);

Eskinder Hailu, Sunnyvale, CA (US);

Masaaki Kaneko, Round Rock, TX (US);

Jieming Qi, Austin, TX (US);

Bin Wan, Pittsburgh, PA (US);

Inventors:

David W. Boerstler, Round Rock, TX (US);

Eskinder Hailu, Sunnyvale, CA (US);

Masaaki Kaneko, Round Rock, TX (US);

Jieming Qi, Austin, TX (US);

Bin Wan, Pittsburgh, PA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 23/00 (2006.01); G01R 29/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A design structure for a circuit for measuring the absolute duty cycle of a signal, is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.


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