The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2011
Filed:
Oct. 30, 2008
Applicants:
Animesh Datta, San Diego, CA (US);
Martin Saint-laurent, Austin, TX (US);
Varun Verma, San Diego, CA (US);
Prayag B. Patel, San Diego, CA (US);
Inventors:
Animesh Datta, San Diego, CA (US);
Martin Saint-Laurent, Austin, TX (US);
Varun Verma, San Diego, CA (US);
Prayag B. Patel, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01);
U.S. Cl.
CPC ...
Abstract
A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitry preventing premature charge or discharge of the output logic circuit input node by the pull-up and/or the pull-down circuit when the clock gating cell is enabled.