The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2011

Filed:

May. 15, 2008
Applicants:

Xiangfeng Duan, Los Angeles, CA (US);

Jian Chen, Mountain View, CA (US);

J. Wallace Parce, Palo Alto, CA (US);

Francisco A. Leon, Palo Alto, CA (US);

Inventors:

Xiangfeng Duan, Los Angeles, CA (US);

Jian Chen, Mountain View, CA (US);

J. Wallace Parce, Palo Alto, CA (US);

Francisco A. Leon, Palo Alto, CA (US);

Assignee:

Nanosys, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.


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