The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2011
Filed:
Jul. 31, 2008
William D. Ramsour, Pflugerville, TX (US);
Samuel I. Ward, Austin, TX (US);
William D. Ramsour, Pflugerville, TX (US);
Samuel I. Ward, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for automatically generating an electronic circuit layout with placed circuit elements includes receiving a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method selects a subset of circuit elements and receives placement inputs. The method generates a first placed layout configuration comprising adjusted placement parameters, based on the received placement inputs, the first placement parameters, and the design parameters. The method assigns absolute placement coordinates for each of the plurality of circuit elements based on the first placed layout configuration. The method generates an electronic circuit layout with placed circuit elements based on the absolute placement coordinates.