The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2011
Filed:
Apr. 15, 2010
Masuyuki Ohta, Mobara, JP;
Kazuhiro Ogawa, Mobara, JP;
Keiichiro Ashizawa, Mobara, JP;
Kazuhiko Yanagawa, Mobara, JP;
Masahiro Yanai, Mobara, JP;
Nobutake Konishi, Mobara, JP;
Nobuyuki Suzuki, Mobara, JP;
Masahiro Ishii, Mobara, JP;
Makoto Yoneya, Hitachinaka, JP;
Sukekazu Aratani, Hitachiohta, JP;
Masuyuki Ohta, Mobara, JP;
Kazuhiro Ogawa, Mobara, JP;
Keiichiro Ashizawa, Mobara, JP;
Kazuhiko Yanagawa, Mobara, JP;
Masahiro Yanai, Mobara, JP;
Nobutake Konishi, Mobara, JP;
Nobuyuki Suzuki, Mobara, JP;
Masahiro Ishii, Mobara, JP;
Makoto Yoneya, Hitachinaka, JP;
Sukekazu Aratani, Hitachiohta, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
An active matrix liquid crystal display device includes first and second substrates, a liquid crystal layer disposed between the first and second substrates, and plural image signal lines and scan signal lines formed on the first substrate. Respective pixel regions are formed by adjacent image signal lines and adjacent scan signal lines, and the respective pixel regions have at least one of a semiconductor layer, a pixel electrode, a counter electrode, and a source electrode which has a high-melting-point metal layer and an aluminum layer formed on the high-melting-point metal layer; wherein the high-melting-point layer enables connection of the semiconductor layer and the pixel electrode, and the pixel electrode is formed between the high-melting-point metal layer and the first substrate; and wherein a part of the scan signal lines positioned between the pixel regions and the gate terminal is covered by an ITO layer electrically connected to the counter electrode.