The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8026577 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 27, 2011

Filed:

Feb. 13, 2008
Applicant:

Takuji Tanaka, Kawasaki, JP;

Inventor:

Takuji Tanaka, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor apparatus according to the present invention includes a first well-region and a second well-region in a semiconductor substrate, and a plurality of transistors formed to the second well-region. Further, the semiconductor apparatus includes a through-hole region that is formed so as to pierce through the first well-region and enables the second well-region to be electrically conductive to the semiconductor substrate on the bottom of the second well. Furthermore, in the semiconductor apparatus, the border of the through-hole region is arranged between the transistors, and is also arranged to be planarity apart from the transistor.


Find Patent Forward Citations

Tanaka, Takuji. (2011). Semiconductor apparatus having a triple well structure and manfacturing method thereof (U.S. Patent No. 8026577). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8026577

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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