The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2011
Filed:
Nov. 13, 2008
Sankaranarayanan Srinivasan, San Jose, CA (US);
Dinesh D. Gaitonde, Fremont, CA (US);
Sankaranarayanan Srinivasan, San Jose, CA (US);
Dinesh D. Gaitonde, Fremont, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Various approaches for improving clock speed for a circuit design. In one embodiment, a graph having nodes and edges that represent the circuit design is generated. The nodes represent flip-flops of the design, the edges represent couplings of data inputs and outputs of the flip-flops, and the edges have associated delay values for respective durations of signal delays of the couplings. A smallest period is determined for which subtracting each delay value from the smallest period and associating the difference with the associated edge does not create a negative cycle in the graph. A path in the graph is selected, the path including selected flip-flops and connecting edges. The circuit design is modified by replacing the selected flip-flops with latches, and the smallest period is output.