The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2011
Filed:
Jun. 30, 2009
Izumi Nitta, Kawasaki, JP;
Izumi Nitta, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
An apparatus that evaluates a layout of a semiconductor integrated circuit by estimating a result of planarization in manufacturing the circuit includes a unit that divides the layout into partial areas, a unit that calculates, for each partial area, at least one of a wiring density in the partial area, a total perimeter length of wirings in the partial area, and a maximum value of differences of wiring densities in adjacent partial areas adjacent to the partial area from the wiring density in the partial area as partial area data, a unit that sets ranges of the wiring density, the total perimeter length, and the maximum value from which a height variation larger than an upper limit value is expected as critical regions based on an equation corresponding to a type of the layout, and a unit that plots the critical regions and the partial area data on a same map.