The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2011
Filed:
Dec. 24, 2008
Jin-mo Yoon, Gyeonggi-do, KR;
In-yeong Kong, Seoul, KR;
Jin-Mo Yoon, Gyeonggi-do, KR;
In-Yeong Kong, Seoul, KR;
LG Display Co., Ltd., Seoul, KR;
Abstract
A gate-in-panel type liquid crystal display device includes first and second substrates spaced apart from and facing each other, the first and second substrates including a display area and a non-display area; gate lines, data lines, thin film transistors and pixel electrodes in the display area on the first substrate, the gate lines and the data lines crossing each other to define pixel regions, the thin film transistors connected to the gate lines and the data lines, the pixel electrodes connected to the thin film transistors; gate pads and data pads in the non-display area on the first substrate, the gate pads and the data pads receiving direct current (DC) signals and alternating current (AC) signals; gate link lines connected to the gate pads and including first gate link lines and second gate link lines, the first gate link lines transmitting the DC signals and disposed to be adjacent to and parallel to each other, the second gate link lines transmitting the AC signals and disposed to be adjacent to and parallel to each other; connection lines connected to the gate link lines; gate circuit blocks connected to the connection lines, the gate circuit blocks generating gate signals using the DC signals and the AC signals and providing the gate signals to the gate lines; and a seal pattern between the first and second substrates and overlapping the gate link lines.