The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2011
Filed:
Feb. 26, 2009
Kazuhide Yokota, Kanagawa, JP;
Hisashi Kurebayashi, Kanagawa, JP;
Kenji Tanaka, Tokyo, JP;
Akira Matsui, Kanagawa, JP;
Yutaka Yoneda, Kanagawa, JP;
Seishin Asato, Chiba, JP;
Takuya Chiba, Tokyo, JP;
Ryota Kosakai, Tokyo, JP;
Kazuhide Yokota, Kanagawa, JP;
Hisashi Kurebayashi, Kanagawa, JP;
Kenji Tanaka, Tokyo, JP;
Akira Matsui, Kanagawa, JP;
Yutaka Yoneda, Kanagawa, JP;
Seishin Asato, Chiba, JP;
Takuya Chiba, Tokyo, JP;
Ryota Kosakai, Tokyo, JP;
Sony Corporation, Tokyo, JP;
Abstract
A solid-state imaging device having: (a) a pixel array with an oblique pixel pattern in which pixels are obliquely disposed, an odd-numbered row vertical signal line in an odd-numbered row vertical signal line group being connected to each column of odd-numbered row pixels and an even-numbered row vertical signal line in an even-numbered row vertical signal line group being connected to each column of even-numbered row pixels; (b) a row selector for separately selecting an odd-numbered row and an even-numbered row of the oblique pixel pattern; (c) an odd-numbered row column processing circuit group including column processing circuits and connected to the odd-numbered row vertical signal line group, for adding signals of the odd-numbered row pixels between columns; (d) an even-numbered row column processing circuit group including column processing circuits and connected to the even-numbered row vertical signal line group, for adding signals of the even-numbered row pixels in pixel columns; and (d) a column selector for selecting the column processing circuits of the odd-numbered row column processing circuit group and the column processing circuits of the even-numbered row column processing circuit group.