The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2011

Filed:

Jun. 17, 2009
Applicants:

Hyung-gu Roh, Gyeongsangnam-do, KR;

Byung-chul Ahn, Seoul, KR;

Hee-dong Choi, Chungnam, KR;

Seong-moh Seo, Gyeonggi-do, KR;

Jun-min Lee, Daegu, KR;

Inventors:

Hyung-Gu Roh, Gyeongsangnam-do, KR;

Byung-Chul Ahn, Seoul, KR;

Hee-Dong Choi, Chungnam, KR;

Seong-Moh Seo, Gyeonggi-do, KR;

Jun-Min Lee, Daegu, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.


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