The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2011

Filed:

Nov. 21, 2008
Applicants:

Chi Bun Chan, San Jose, CA (US);

Jingzhao Ou, Sunnyvale, CA (US);

Jeffrey D. Stroomer, Lafayette, CO (US);

Inventors:

Chi Bun Chan, San Jose, CA (US);

Jingzhao Ou, Sunnyvale, CA (US);

Jeffrey D. Stroomer, Lafayette, CO (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A computer-implemented method of circuit design can include receiving clock frequency constraints defining relationships between clock frequencies of a plurality of clock domains of a circuit design specified within a high-level modeling system () and receiving a cost function that is dependent upon the clock frequencies of the plurality of clock domains (). A feasibility result can be determined according to the clock frequency constraints and the cost function (). The feasibility result can indicate whether a clock frequency assignment exists that specifies a clock frequency for each of the plurality of clock domains that does not violate any clock frequency constraint. The feasibility result can be output ().


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