The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2011
Filed:
May. 19, 2008
Herve Alexanian, San Jose, CA (US);
Chien-chun Chou, Saratoga, CA (US);
Vida Vakilotojar, Mountain View, CA (US);
Grigor Yeghiazaryan, Yerevan, AM;
Herve Alexanian, San Jose, CA (US);
Chien-Chun Chou, Saratoga, CA (US);
Vida Vakilotojar, Mountain View, CA (US);
Grigor Yeghiazaryan, Yerevan, AM;
Sonics, Inc., Milpitas, CA (US);
Abstract
Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction.