The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2011
Filed:
Oct. 01, 2007
Fook-luen Heng, Yorktown Heights, NY (US);
Mark A. Lavin, Katonah, NY (US);
Jin-fuw Lee, Yorktown Heights, NY (US);
Thomas Ludwig, Sindelfingen, DE;
Rama Nand Sing, Bethel, CT (US);
Fanchieh Yee, Fishkill, NY (US);
Fook-Luen Heng, Yorktown Heights, NY (US);
Mark A. Lavin, Katonah, NY (US);
Jin-Fuw Lee, Yorktown Heights, NY (US);
Thomas Ludwig, Sindelfingen, DE;
Rama Nand Sing, Bethel, CT (US);
Fanchieh Yee, Fishkill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.