The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2011

Filed:

Mar. 18, 2008
Applicant:

Kazuo Tamaki, Kitakatsuragi-gun, JP;

Inventor:

Kazuo Tamaki, Kitakatsuragi-gun, JP;

Assignee:

Sharp Kabushiki Kaisha, Osaka-Shi, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

The semiconductor device includes a plurality of semiconductor chips, and a circuit substrate having a substantially rectangular outer shape. The semiconductor device is an MCM having an MCM packaging structure in which the plurality of semiconductor chips are juxtaposed on the semiconductor chip mounting surface of the circuit substrate, and the semiconductor chip mounting surface is covered by a sealing resin along an outer edge of the circuit substrate so that the plurality of semiconductor chips are sealed. The thickness of the semiconductor chip to be mounted so as to traverse a center line has a thicker thickness in a direction perpendicular to the semiconductor chip mounting surface than the thickness of any of the other semiconductor chips which is mounted on the semiconductor chip mounting surface, the center line being defined an intersection of (i) a longitudinal cross section which divides the semiconductor chip mounting surface into two in a longitudinal direction of the semiconductor chip mounting surface and (ii) a transverse cross section which divides the semiconductor chip mounting surface into two in a transverse direction of the semiconductor chip mounting surface. This enables to suppress the warpage generated in the semiconductor device, and to reduce inadequate connection occurred due to the warpage in the semiconductor device.


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