The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2011
Filed:
Dec. 21, 2010
Toshikazu Matsui, Ibi-gun, JP;
Yasuyuki Sayama, Anpachi-gun, JP;
Hiroki Eto, Ora-gun, JP;
Takumi Hosoya, Isesaki-shi, JP;
Toshikazu Matsui, Ibi-gun, JP;
Yasuyuki Sayama, Anpachi-gun, JP;
Hiroki Eto, Ora-gun, JP;
Takumi Hosoya, Isesaki-shi, JP;
SANYO Semiconductor Co., Ltd., Gunma, JP;
Semiconductor Components Industries, LLC, Phoenix, AZ (US);
Abstract
The invention provides a method of manufacturing a semiconductor device at low cost in which the gate insulation film having a trench structure is not damaged by arsenic ions when the emitter layer or the like is formed and the insulation breakdown voltage is enhanced. A gate electrode made of polysilicon formed in a trench is thermally oxidized in a high temperature furnace or the like to form a thick polysilicon thermal oxide film on the gate electrode. Impurity ions are then ion-implanted to form an N type semiconductor layer that is to be an emitter layer or the like. At this time, the polysilicon thermal oxide film is formed thicker than the projected range Rp of impurity ions in the silicon oxide film for forming the N type semiconductor layer as the emitter layer or the like by ion implantation. This prevents a gate insulation film between the gate electrode and the N type semiconductor layer from being damaged by the impurity ions.