The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2011
Filed:
Jul. 01, 2008
Markus Buehler, Weil im Schoenbuch, DE;
Juergen Koehl, Weil im Schoenbuch, DE;
Markus Olbrich, Langenhagen, DE;
Philipp Panitz, Lehrte, DE;
Markus Buehler, Weil im Schoenbuch, DE;
Juergen Koehl, Weil im Schoenbuch, DE;
Markus Olbrich, Langenhagen, DE;
Philipp Panitz, Lehrte, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin and a receiving pin being coupled by at least one loop, the loop comprising a first branching path and a second branching path electrically parallel to the first branching path, wherein at least a first and a second branching point connect the branching paths. The method comprises the steps of disconnecting each branching path once at a time at a specific point in said the at least one loop which connects a driver to at least one specific receiving pin; calculating a delay value of a signal connection between the driver pin and each of the receiving pin for each of the disconnected branching paths of each loop; storing maximum and/or minimum calculated delay values; and applying at least one of the delay values for static timing analysis of the electronic circuit.