The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2011

Filed:

Dec. 19, 2007
Applicants:

Takahiko Sato, Kawasaki, JP;

Toshiya Uchida, Kawasaki, JP;

Tatsuya Kanda, Kawasaki, JP;

Tetsuo Miyamoto, Kawasaki, JP;

Satoru Shirakawa, Kawasaki, JP;

Yoshinobu Yamamoto, Kawasaki, JP;

Tatsushi Otsuka, Kawasaki, JP;

Hidenaga Takahashi, Kawasaki, JP;

Masanori Kurita, Kawasaki, JP;

Shinnosuke Kamata, Kawasaki, JP;

Ayako Sato, Kawasaki, JP;

Inventors:

Takahiko Sato, Kawasaki, JP;

Toshiya Uchida, Kawasaki, JP;

Tatsuya Kanda, Kawasaki, JP;

Tetsuo Miyamoto, Kawasaki, JP;

Satoru Shirakawa, Kawasaki, JP;

Yoshinobu Yamamoto, Kawasaki, JP;

Tatsushi Otsuka, Kawasaki, JP;

Hidenaga Takahashi, Kawasaki, JP;

Masanori Kurita, Kawasaki, JP;

Shinnosuke Kamata, Kawasaki, JP;

Ayako Sato, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.


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