Zero-delay serial communications circuitry for serial interconnects

Abstract

Circuitry and methods for supporting serial communications over serial interconnects between circuit modules are provided. A data recovery circuit receives incoming serial data from the serial interconnect path with zero delay. The data recovery circuit includes a data sampler that samples the incoming serial data using a multiphase clock. Data samples are provided to a multiplexer that selects an optimum sampled data signal to use as a recovered data signal. The multiplexer has a control input that receives a phase pointer signal. Control circuitry in the data recovery circuit analyzes the sampled data signals and a current value of the phase pointer to compute a clock phase shift error. If the clock phase shift error exceeds a predetermined value, the phase pointer signal can be updated. The data recovery circuit may be implemented using hardwired circuitry or programmable logic.