The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2011
Filed:
Jun. 23, 2009
Masayoshi Nakayama, Shiga, JP;
Kazuyuki Kouno, Osaka, JP;
Reiji Mochida, Osaka, JP;
Hoshihide Haruyama, Kyoto, JP;
Masayoshi Nakayama, Shiga, JP;
Kazuyuki Kouno, Osaka, JP;
Reiji Mochida, Osaka, JP;
Hoshihide Haruyama, Kyoto, JP;
Panasonic Corporation, Osaka, JP;
Abstract
In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor.