The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2011
Filed:
Mar. 21, 2011
Amlan Majumdar, White Plains, NY (US);
Gen Pei, Yorktown Heights, NY (US);
Zhibin Ren, Hopewell Junction, NY (US);
Dinkar Singh, Chicago, IL (US);
Jeffrey W. Sleight, Ridgefield, CT (US);
Amlan Majumdar, White Plains, NY (US);
Gen Pei, Yorktown Heights, NY (US);
Zhibin Ren, Hopewell Junction, NY (US);
Dinkar Singh, Chicago, IL (US);
Jeffrey W. Sleight, Ridgefield, CT (US);
International Business Machines Corporation, Armonk, NY (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.