The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2011
Filed:
Nov. 20, 2009
Samuel J. Guido, Dearborn, MI (US);
Jeremy W. Brodt, Plano, TX (US);
Jeffrey T. Sieber, Livonia, MI (US);
Samuel J. Guido, Dearborn, MI (US);
Jeremy W. Brodt, Plano, TX (US);
Jeffrey T. Sieber, Livonia, MI (US);
Renesas Electronics America Inc., Santa Clara, CA (US);
Abstract
An apparatus is disclosed that includes first and second circuits coupled together via a bus, an input pin configured to receive an analog input signal, a digital-to-analog (DAC) convertor configured to convert a multibit reference signal into an analog reference signal, a comparator circuit coupled to the bus, an output of the DAC and to the input pin. The comparator circuit is configured to receive the analog reference signal from the DAC and the analog input signal, and configured to generate a first digital signal set to a first state if the analog reference signal is greater in magnitude than the analog input signal, or set to a second state if analog reference signal is lower in magnitude than the analog input signal. The comparator circuit is also configured to transmit the first digital signal to the first circuit via the bus. The first circuit in turn is configured to receive the first digital signal. In response to receiving the first digital signal, the first circuit is configured to generate a second digital signal set to the first or second state depending on whether the received first digital signal is set to the first or second state. The second circuit is configured to receive the second digital signal from the first circuit via the bus.