The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2011

Filed:

Dec. 17, 2007
Applicants:

Paul L. Master, Sunnyvale, CA (US);

Eugene Hogenauer, San Carlos, CA (US);

Walter James Scheuermann, Saratoga, CA (US);

Inventors:

Paul L. Master, Sunnyvale, CA (US);

Eugene Hogenauer, San Carlos, CA (US);

Walter James Scheuermann, Saratoga, CA (US);

Assignee:

QST Holdings LLC, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/16 (2006.01); G06F 15/177 (2006.01); G06F 15/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides an adaptive integrated circuit. The various embodiments include a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.


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