Semiconductor memory device including memory cell array having memory cells using floating body transistors

Abstract

A semiconductor memory device includes a memory cell array, which includes a cell array having multiple cell blocks. Each cell block includes source and word lines arranged in one direction, bit lines arranged in a perpendicular direction, and memory cells having corresponding floating bodies. Adjacent memory cells share source or drain regions to form common source or drain regions, respectively. The source regions are arranged in a word line direction and connected to corresponding source lines, and the drain regions are arranged in the bit line direction and connected to corresponding bit lines. Gates of the memory cells are arranged in the word line direction and are connected to form the word lines. The source lines are formed on a layer of the word lines, and the bit lines are formed at a different layer to be insulated from the word and source lines.